1. Field of the Invention
Example embodiments of the present invention relate to a memory system and semiconductor memory device which generates an output data strobe signal having a preamble signal and a method for generating an output data strobe signal.
2. Description of the Related Art
Conventionally, a memory system may include a memory controller and a semiconductor memory device. Input/output data strobe signals may be generated together with data to provide accurate timing of input/output data during a data transmission between a memory controller and a semiconductor memory device.
For example, in a double data rate, quadruple data rate, etc., semiconductor device, data input/output may be performed in synchronization with a rising edge and/or falling edge of a clock signal. The input/output data strobe signals may be generated in synchronization with a clock signal. The semiconductor device may receive sampled input data with the input data strobe signal during a write operation and may output data with an output data strobe signal during a read operation.
However, as operation speed of the memory system increases, a frequency of the clock signal may increase, and thus the output data strobe signal which may be generated in synchronization with the clock signal and may be generated during a read operation may not swing stably from a first output voltage to a second output voltage during an initial generating stage. As a result, the output data strobe signal and the data which are generated initially may not coincide.
Due in part to the forgoing, a semiconductor memory device may generate a preamble signal during a predetermined cycle (fixed, for example) before generating a strobe signal of the output data strobe signal, thereby possibly providing stable swing during the initial stage of strobe signal generation. As a result, generation timing between the output data strobe signal and transmitted data may coincide. The preamble signal may be synchronous with the clock signal before the strobe signal of the output data strobe signal is generated. However, the initially generated preamble signal may not be synchronous with the clock signal due to an unstable swing and may be toggled during a predetermined cycle (fixed, for example) to gradually become synchronous with the clock signal.
The memory controller may be connected to a plurality of semiconductor memory devices and an output data strobe signal line may be commonly connected to an output data line. If a cycle number of the preamble signal of the data strobe signal of a plurality of semiconductor memory devices is fixed, a problem may occur because the read operation of a first semiconductor memory device may be performed immediately or approximately immediately after read operation of a second semiconductor memory device. Because the preamble signal of the output data strobe signal may be generated from the second semiconductor memory device while the strobe signal of the output data strobe signal may be generated from the first semiconductor memory device, a collision may occur between the strobe signal of the first semiconductor device and the preamble signal of the output data strobe signal of the second semiconductor device.